Intel Threading Tools Events

The Future: What Multi-Core Means to the High Performance Computing Developer Marketplace


Venue Date Time Venue
University of Technology Sydney, Room 5B.03.29, Level 3, Block B, UTS Building 5, Markets Campus, Quay Street, Haymarket Mon, 08/12/2008 2:30 PM Request Booking
University of Melbourne, Room 2.06, ICT Building, 111 Barry St, Carlton Thu, 11/12/2008 2:30 PM Request Booking

James Reinders of Intel will show you how to get the most out of your software on multi-core systems all the way up to high performance clusters.

Overview

A software revolution is underway, triggered by the shift to multi-core hardware architectures. Intel has unprecedented programs ranging from working with professors around the world, to Intel’s leadership in software development tools for multi-core. A recent Evans Data survey found that in markets surveyed, Intel “dominated” the multi-core software development tools. Reinders will share examples of what Intel is learning, including some surprising and generally encouraging results. Experiences in this last year, including open sourcing Intel Threading Building Blocks, have given Intel unique insight into what software developers are actually doing. Reinders will extrapolate from these experiences and provide concrete ideas on where this is going to take us, and how Intel products fit into software developers’ needs.

Presenter

James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to a number of projects, including the world's first TeraFLOP supercomputer (ASCI Red), compilers and architecture work for the iWarp, Pentium Pro, Pentium II, Itanium, and Pentium 4 processors. He has years of experience in processor architecture, optimizing compilers, parallel computer architecture, and making products for software developers.

James is an expert in the area of parallelism, Intel's leading spokesperson on tools for parallelism, and author of the O'Reilly Nutshell book on the C++ extensions for parallelism provided by the popular Intel Threading Building Blocks. He has decades of experience with high degrees of parallelism having worked on groundbreaking compilers and architectures such as the systolic arrays WARP and iWarp. James is author and co-author of several books in addition to the Threading Building Blocks Nutshell book.

 

Selected highlights of James' Bio

  • A thought leader on Parallel computing
  • Contributor to ASCI Red (first TeraFLOP supercomputer)
  • Compiler Development experince
  • Architecture engineering for Intel processors
  • Author of O'Reilly 'Intel Threading Building Blocks in a Nutshell'
  • Author of 'VTune Performance Analyzer Essentials.'
  • Regular columnist for 'The Gauntlet', found online at go-parallel.com

 

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